1. Field of the Invention
The invention relates to a method of fabricating a DRAM device, and more particularly to a method of fabricating a DRAM device which has an improved refresh characteristic through a decrease of a junction leakage.
2. Related Prior Art
In a dynamic random access memory (DRAM) including a capacitor and a transistor, the transistor, in general, serves as a switching device which stores or discharges a charge. Since the capacitor of the DRAM discharges the charges therein naturally with the lapse of the time, the capacitor must be recharged per a selected period. Such a recharge is referred as "refresh". So as to refresh the DRAM, it is required to connect a refresh circuit to the DRAM.
FIG. 1a is a cross-sectional view of the DRAM. On a portion of a semiconductor substrate 1 having a P type well 1A is formed a field oxide layer 2 by a known LOCOS technique. On a portion of the surface of the semiconductor substrate 1 between two adjacent field oxide layers is formed a gate oxide 3A. Following the formation of the gate oxide 3A, a gate electrode material, for example a polysilicon with a doped impurity is deposited with a selected thickness on the resultant structure of the semiconductor device and is then patterned to form a gate electrode 3. To both sides of the gate electrode 3 on the semiconductor substrate are implanted impurity ion, for example, phosphorus ion, with a dose of 2.times.10.sup.13 ions /cm.sup.2, forming a source region 4A and a drain region 4B. Here the impurity is a counter type to that of the substrate. So as to isolate the gate electrode 3 from a capacitor to be formed in the future step an interlayered insulating layer 5 is formed on the entire surface of the resultant structure having a transistor. A contact hole 6 for connecting the transistor with a storage node electrode of the capacitor is formed by etching a portion of the interlayered insulating layer 6. So as to obtain a sufficient width of the contact hole during the formation of the contact hole, a portion of bird's beak formed at both sides of the field oxide layer is etched. Furthermore, so as to compensate the defects of the semiconductor substrate occurred during the formation of the contact hole, a selected plug ion, for example phosphorus ion is ion-implanted.
Next, a polysilicon layer doped with a phosphorus ion is formed on the resultant and is then patterned to form a storage node electrode(not shown). Afterwards, in a known manner the steps of forming a dielectric film on the top surface of the storage node electrode and of forming a plate node electrode on the top surface of the dielectric film are carried out.
FIG. 1b is a graph showing a concentration distribution of an impurity according to a depth of a source region of the DRAM device shown in FIG. 1a. Wherein a horizontal axis represents the depth of the source region and a vertical axis represents a concentration of an impurity. A curve A shows a doping profile of P type well when a first conductive type impurity is used. A curve B shows a doping profile of a junction region of the substrate when a second conductive impurity is used. A curve C shows a concentration difference between the curve A and the curve B. The curve A shows that a concentration distribution of an impurity is almost even until a selected depth of the semiconductor device. The curve B shows that the concentration of impurity has a peak value near the top surface of the semiconductor substrate and decreases from the peak value according to the increase of the depth of the substrate. The curve C shows that it decreases rapidly at the intersecting portion of the curve A and the curve B, i.e., near a junction interface and after that has almost equal to that of P well.
However, since an impurity concentration contained in the storage node electrode is higher than that of a junction region, the impurity of the storage node out-diffuses into the junction region. At this time, the impurities within the storage node electrode diffuse mainly into a plug ion implantation region and a strong electrical field is thereby formed at the source region since the source region becomes asymmetrical. The strong electrical field generates a large amount of leakage current due to an impact ionization. The leakage current lowers the refresh characteristic, a yield and reliability of the DRAM cell.